The present invention relates to a frequency detector and a phase-locked loop (PLL) circuit that can detect a frequency difference using the detector built in the circuit.
A PLL circuit is an important circuit applicable to various types of LSI systems of today. A known PLL circuit includes a PLL and a frequency controller. The PLL is made up of phase detector, charge pump, low-pass filter (LPF), voltage-controlled oscillator (VCO) and frequency divider. The frequency controller is provided to eliminate a frequency deviation from the PLL. In the PLL, if the gain of the VCO is decreased to enhance the noise immunity of the PLL, then the output frequency range of the VCO shrinks correspondingly, thus narrowing the frequency locking range of the PLL unintentionally. To avoid this problem, the PLL circuit is equipped with not only the phase detector that compares the phases of reference and oscillated clock signals to each other but also the frequency controller including a frequency detector that detects a frequency difference between these clock signals. That is to say, the PLL circuit utilizes two feedback loops so as not to narrow the frequency locking range. Specifically, in this case, the additional feedback loop, formed by the frequency detector, should have an increased gain, while the original phase-locked loop should have a decreased gain.
An exemplary known frequency detector was disclosed by D. S H. Wolaver in xe2x80x9cPhase-Locked Loop Circuit Designxe2x80x9d, Section 4-12, pp. 68-75, Prentice Hall (1991). The Wolaver""s frequency detector includes a three-state phase detector and first and second additional detectors called xe2x80x9cslip detectorsxe2x80x9d. Responsive to a rising edge of a first or second input clock signal, the phase detector alternates among three states, thereby outputting first and second phase difference pulse signals. Each of the pulse signals represents a phase difference between the two input clock signals. The first slip detector includes two cascaded latches, receiving the first phase difference pulse signal at its clock input, and a device for delaying the first input clock signal. The second slip detector includes two cascaded latches, receiving the second phase difference pulse signal at its clock input, and a device for delaying the second input clock signal.
The known frequency detector uses the phase difference pulse signals of the phase detector as clock signals for activating the initial-stage latches of the slip detectors. Accordingly, if the pulse width of the phase difference pulse signals is too narrow to set the initial-stage latches of the slip detectors, then the frequency difference will be detected erroneously.
In addition, each of the delay devices for the slip detectors needs a large number of inverters. Accordingly, these inverters might generate noise and adversely affect the operation of the PLL circuit. Furthermore, the delay should be controlled so strictly that the operating range of the PLL circuit might be limited.
It is therefore an object of the present invention to provide a frequency detector that is implementable using a much simpler circuit configuration and yet needs no such strict delay control.
Another object of the present invention is to provide a phase-locked loop circuit that can detect a frequency difference by using the frequency detector built in it.
To achieve these objects, a frequency detector according to the present invention is realized just by connecting first and second latches to a three-state phase detector of the known type.
Specifically, in the present invention, the three-state phase detector includes first and second input terminals and first and second output terminals. To detect a phase difference between first and second input clock signals presented to the first and second input terminals, respectively, the phase detector outputs first and second phase difference pulse signals through the first and second output terminals, respectively, by alternating among the following three states. If an effective edge of the first input clock signal is presented to the phase detector in a neutral state, then the phase detector is set to change into a first phase detection state. If an effective edge of the second input clock signal is presented to the phase detector in the neutral state, then the phase detector is set to change into a second phase detection state. And if effective edges of the first and second input clock signals are presented to the phase detector in this order or vice versa, then a reset signal is generated and the phase detector is reset and get back to the neutral state responsive to the reset signal. The first latch latches the signal, which has been output through the first output terminal of the phase detector, responsive to an effective edge of the first input clock signal, and is reset responsive to the reset signal of the phase detector. The first latch outputs a first frequency difference pulse signal if two edges of the first input clock signal have been presented to the phase detector consecutively with no effective edges of the second input clock signal presented between the two edges. The second latch latches the signal, which has been output through the second output terminal of the phase detector, responsive to an effective edge of the second input clock signal, and is reset responsive to the reset signal of the phase detector. The second latch outputs a second frequency difference pulse signal if two edges of the second input clock signal have been presented to the phase detector consecutively with no effective edges of the first input clock signal presented between the two edges.
According to the present invention, a frequency detector is implementable just by connecting two latches to a three-state phase detector of the known type. Thus, the inventive frequency detector can be of a much smaller circuit size than the known ones. In addition, according to the present invention, the phase difference pulse signals output from the three-state phase detector are not used as clock signals that activate the first-stage latches of slip detectors unlike the known frequency detector. Instead, in the present invention, the input clock signals for the phase detector are also used as clock signals for activating the two additional latches. Thus, the inventive frequency detector can have its operation stabilized even without controlling delays, for example. That is to say, the inventive frequency detector can advantageously be designed much more easily, and still can operate much more stably, than the known frequency detector